1. Field of the Invention
The present invention relates to adjusting methods of an arithmetic multiplying circuit, a drive circuit, and a phase margin.
2. Related Art
As a liquid crystal panel (electrooptical device) used in electronic equipment such as a mobile phone, there are conventionally known a liquid crystal panel of a simple matrix system and a liquid crystal panel of an active matrix system using a switching element such as a thin film transistor (hereinafter abbreviated as TFT).
While the simple matrix system is advantageous in that its low power consumption can be easily implemented, its disadvantage lies in its difficulty to provide multiple colors and animation display. On the other hand, the active matrix system is advantageous in that it is suited for multiple colors and animation displays, whereas its disadvantage lies in its difficulty to provide low power consumption.
In recent years, demand for multi-color, animation displays is high to provide high quality images in electronic equipment of a portable type such as a mobile phone. Consequently, in lieu of the liquid crystal panel of the simple matrix system thus far used, the liquid crystal panel of the active matrix system is being used now.
In the liquid crystal panel of the active matrix system, it is preferable to set up an arithmetic amplifying circuit (operating amplifier) that functions as an output buffer in a data line drive circuit driving a data line of the liquid crystal panel.
Prior-art arithmetic amplifying circuits of this type included a differential amplifying circuit and an output circuit and fed back an output of the output circuit to the differential amplifying circuit. Because of a large drive capacity of the output circuit, a reaction rate of the output circuit was extremely fast as compared to the reaction rate of the differential amplifying circuit, a capacitor for preventing oscillation was inserted to prevent oscillation in a pass that fed back the output of the output circuit (refer to Japanese Unexamined Patent Publication No. Hei6-149188 and Japanese Unexamined Patent Publication No. 2003-229725).
However, in the conventional configuration, inasmuch as the capacitor for preventing oscillation was indispensable in the arithmetic amplifying circuit, it was difficult to reduce circuit size. Particularly in a case where application is made to the data line drive circuit as the output buffer, the arithmetic amplifying circuit is set up, for example, for every 720 data lines, thereby enlarging a chip area and causing high cost.
Also, the reaction rate of the output circuit, which is extremely fast as compared to the reaction rate of the differential amplifying circuit, becomes slow with an increase in load capacity. As a result, the reaction rate of the arithmetic amplifying circuit and the reaction rate of the output circuit come closer to each other, making it easy for oscillation to occur. This shows that, as a size of a display panel expands, an output load of the arithmetic amplifying circuit that functions as the output buffer also increases, so that margin for oscillation diminishes.
Further, it is necessary to change a volume value of the capacitor for oscillation prevention, together with the output load, when a capacitor is formed inside the circuit, the switching element and the like will be newly needed to perform trimming of the capacitor. In addition, the capacitor characteristics themselves deteriorate.
The present invention has been made in view of the above-mentioned technical problems. It is an object thereof to provide methods of adjusting the arithmetic amplifying circuit, the drive circuit, and the phase margin which prevent oscillation at low cost while increasing drive capacitive load.